Speedgoat

General

Analog input section (at 25ºC)

Configuration: 64 single-ended analog input channels, dedicated A/D converter per channel
Differential inputs: Software selectable differential processing of channel pairs
Resolution: 16 Bits (0.0015 percent of FSR)
Channel conversion time: 5µs, maximum
Sampling mode: Simultaneous; 1, 2, 4, 8, 16, 32, or 64 channels
Voltage ranges: Driver configurable as ±10V, ±5V, ±2.5V, 0-10V, or 0-5V
Input impedance: 750kOhm typical
Bias current: 1µA, maximum (±2.5V range), 4µA, maximum (±10V range)
Crosstalk rejection: 85dB, DC-50kHz
Input noise (0.01-50kHz): 0.5mVRMS, typical, all ranges
Input bandwidth (-3dB): DC to 120kHz typical
Overvoltage protection: ±40V with power applied, ±25 Volts with power removed.
DC accuracy (maximum composite error after autocalibration):

±10V range: ± 1.5mV (midscale accuracy), ± 2.8mV (full scale accuracy)

±5V range: ± 1.4mV (midscale accuracy), ± 2.5mV (full scale accuracy)

±2.5V range: ± 0.9mV (midscale accuracy), ± 1.5mV (full scale accuracy)

0-10V range: ± 1.8mV (midscale accuracy), ± 3.0mV (full scale accuracy)

0-5V range: ± 1.2mV (midscale accuracy), ± 2.7mV (full scale accuracy)

Integral nonlinearity: ±0.008 percent FSR (FSR = fullscale range; e.g.: 20V on ±10V range)
Differential nonlinearity: ±0.004 percent FSR

Customer quote

"Up and running in less than a day!"

Darren Hartman,
HUSCO International

News

Automatic HDL code generation for Speedgoat's FPGA-based I/O modules for Real-Time Simulation and Testing on FPGAs
(08-April-2011) Read more

Performance real-time target machine now supports i5 multi-core CPUs with clock rates up to 3.6GHz
(08-April-2011) Read more

Mobile real-time target machine now supports dual-core CPUs with clock rates up 2.16GHz
(14-March-2011) Read more

New 18-bit analog input I/O module with up to 32 channels
(03-January-2011) Read more

MathWorks and Speedgoat launch xPC Target Turnkey solution(25-August-2010) Read more