IO108 data sheet

General

  • Form factor: 32-bit 33/66MHz PMC (PCI)
  • Operating temperature: 0 to 65ºC
  • Relative operating humidity: 0 to 80%, non-condensing
  • EMI: EMI shield on component side
  • Power consumption: 5.5W typical, 7.5W maximal

Analog output section (at 25ºC)

  • Configuration: 8 3-wire balanced differential analog outputs, dedicated D/A converter per channel, each 3-wire output consists of complimentary High and Low signal lines with an Output Return as the center (balance) reference.
  • Resolution: 16 Bits (0.0015 percent of FSR)
  • Update time: 2.2µs per channel
  • Settling time: 5µs to 0.1%, 8µs to 0.01%
  • Voltage ranges: ±10V, ±5V, ±2.5V, or ±1.25V
  • Output resistance: 1.0Ohm maximum
  • Output protection: Withstands sustained short-circuiting to ground
  • Load current: ±3mA maximum, ±2mA recommended for minimum crosstalk and line loss
  • Load capacitance: Stable with 0 to 10,000pF shunt capacitance, all ranges, all loads
  • Noise : 1.3mVRMS, 10Hz-10MHz
  • Glitch impulse: ±2.5V range: 3nV-Sec max, ±10V range: 8nV-Sec
  • Remote sensing: Single input pin compensates for ground potential at load. Max range ±1.0V. Enabled or disabled through software. Correction ±1%. Input resistance: 15kOhm typical.
  • DC Accuracy (Max error, no-load):
  • ±10V range: ± 2.4mV (midscale accuracy), ± 3.3mV (full scale accuracy)

    ±5V range: ± 1.7mV (midscale accuracy), ± 2.2mV (full scale accuracy)

    ±2.5V range: ± 1.4mV (midscale accuracy), ± 1.6mV (full scale accuracy)

    ±1.25V range: ± 1.25mV (midscale accuracy), ± 1.4mV (full scale accuracy)

  • Output balance: 10mV maximum High/Low unbalance
  • Bandwidth: >300kHz, typical -3dB
  • Crosstalk rejection: 80 dB minimum, DC - 50kHz
  • Integral nonlinearity: ±0.007 percent of FSR, maximum
  • Differential nonlinearity: ±0.003 percent FSR, maximum

Customer quote

"Up and running in less than a day!"

Darren Hartman,
HUSCO International

News

Automatic HDL code generation for Speedgoat's FPGA-based I/O modules for Real-Time Simulation and Testing on FPGAs
(08-April-2011) Read more

Performance real-time target machine now supports i5 multi-core CPUs with clock rates up to 3.6GHz
(08-April-2011) Read more

Mobile real-time target machine now supports dual-core CPUs with clock rates up 2.16GHz
(14-March-2011) Read more

New 18-bit analog input I/O module with up to 32 channels
(03-January-2011) Read more

MathWorks and Speedgoat launch xPC Target Turnkey solution(25-August-2010) Read more

Read more news

Newsletter subscription