Speedgoat

CAP FPGA code module

The CAP (FPGA code) module is based on a 32-bit counter clocked at 33MHz and requires one digital I/O line (Input) set as an input.

The physical pulse train of which certain characteristics should be measured is connected to the Input line. Based on the Start event (Up: low-to-high transition or Down: high-to-low transition) the counter starts counting up from 0. Based on the Stop event ((Up: low-to-high transition or Down: high-to-low transition) the current counter value is latched into an output register which can then be read by the xPC Target driver block and the counter is reset to 0 for the next Start-Stop events. Depending on the Start and Stop event type the CAP module can return the following characteristics of a pulse train:

Start=Up,Stop=Down: Duration of High pulse
Start=Down,Stop=Up: Duration of Low pulse
Start=Up,Stop=Up: Period between Low-to-High transitions
Start=Down,Stop=Down: Period between High-to-Low transitions

Here a few examples for what one or several CAP modules can be used for:

Set the Start event to Up and the Stop event to Up or the other way around to measure the period of a pulse train.
Set the Start event to Up and the Stop event to Down to measure the duty cycle of a PWM signal based on the High pulse and assuming a constant period.
Set the Start event to Down and the Stop event to Up to measure the duty cycle of a PWM signal based on the Low pulse and assuming a constant period.
Use two CAP modules (2 Input lines connected to the same physical pulse train). One CAP module reacts on events Start=Up and Stop=Down to measure the High pulse duration and the other reacts on events Start=Up and Stop=Up to measure the period. The ratio of the first and second count value then provides the duty cycle of a pulse train where the period is not assumed to be constant.

The minimum duration the CAP module can measure is 2 x 1/33e6 = 60.61ns and the maximum duration is (2^32-1) x 1/33e6 = 130.15s.

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