PWM FPGA code module

At its core a PWM module contains a 32-bit deep Counter and the PWM Control logic. The input clock for the Counter and PWM Control logic is 33MHz. The PWM module requires three digital I/O lines (A-Output, B-Output, Trigger-Output) set as outputs.

The PWM Control logic is implemented as a state machine.

The PWM generation can either be in mode Stopped or Started. The default mode after target application download is Stopped.

If in mode Stopped output signals A, B, and Trigger are:

  • A-Output: Set to the level defined by A-output Stop State
  • B-Output: Set to the level defined by B-output Stop State
  • Trigger-Output: Low at all times, no Trigger pulses are generated

If PWM generation is started (mode Started) the PWM Control logic starts cycling through a loop of PWM cycles which repeats itself until the mode Stopped gets active again. The PWM generation always completes its current cycle even if mode Stopped is set during the cycle.

When mode Started is entered the output signals are:

  • A-Output: Set to the level defined by A-output Start State
  • A-Output: Set to the level defined by A-output Start State
  • Trigger-Output: Low

Furthermore the Counter is loaded with value 0, and the current A, B, and Period Compare values are latched (held constant during a cycle). The Counter then counts up until the Period Compare value is reached. If reached the Counter changes direction and counts down until count 0 is reached. Then the cycle restarts. The Counter therefore runs in Triangle mode.

The maximum count value reached is actually one count higher than the Period Compare value. Furthermore the Period Compare value actually defines half of the period of the PWM output signals. Assuming a given PWM frequency (f) of a 1000Hz, the Period Compare value has to be set to: Period-Compare= round( 33e6 / (2 * f) ) -1 = 16499

If the count value becomes equal to the latched A-Compare value the Control logic toggles (low->high resp. high->low) the A-output signal. The toggling takes place one count later than the A-Compare value. If the A-Compare value is smaller than the Period-Compare value the equality is true twice during each cycle (once during count up and one during count down).

If the count value becomes equal to the latched B-Compare value the Control logic toggles (low->high resp. high->low) the B-output signal. The toggling takes place one count later than the B-Compare value. If the B-Compare value is smaller than the Period-Compare value the equality is true twice during each cycle (once during count up and one during count down).

The A-Compare, B-Compare, and Period-Compare values are also shadowed. This means that the target machine’s driver code can write one or several of these values fully asynchronously (at any time) independently of the current state of the PWM Control state machine. The driver code then issues an Update command to make the shadowed values the new values which are then latched the next time a PWM cycle starts.

When mode Stopped is entered again the current PWM cycle completes and the output signals become again:

  • A-Output: Set to the level defined by A-output Start State
  • A-Output: Set to the level defined by A-output Start State
  • Trigger-Output: Low

The A-output Start State, A-output Stop State, B-output Start State, and B-output Stop State values are not shadowed and don’t have to be shadowed because they don’t span over several 32-bit registers and are also combined in a single 32-bit register when more than one PWM channel is accessed. Also, the driver writes these registers before the Stop/Start register is written during a driver’s sample hit. This means that the current State values become active in the PWM Generation before the driver may change the mode from Stopped to Started or vice versa.

From a PWM generation application perspective the A-Compare, B-Compare, Period- Compare, and various State values can be used in the following ways:

  • For single output PWM generation, set the A-Output Start State value to the required level, set and keep the Period-Compare value constant, and update the A-Compare value during run-time.
  • For a single output of ‘flexible’ pulse train generation, set the A-Output Start State value to the required level, and update the A-Compare and Period-Compare values during run-time (frequency modulation).
  • For dual output PWM generation with same PWM frequency, set the A-Output Start State value and B-Output Start State value to the required level, set and keep the Period-Compare value constant, and update the A-Compare value and B-Compare value during run-time.
  • For single output PWM half-bridge generation, set the A-Output Start State value to the required level, the B-Output Start State value to the inverse level, set and keep the Period-Compare value constant, and update the A-Compare value and B-Compare value during run-time with the same value.
  • For single output PWM half-bridge generation with dead-band (Tdead), set the AOutput Start State value to the required level, the B-Output Start State value to the inverse level, set and keep the Period-Compare value constant, and update the ACompare value and B-Compare value according to A-Compare = AB-Compare - round( 33e6 * Tdead / 2) and B-Compare = AB-Compare + round( 33e6 * Tdead / 2)
  • For multi-phase PWM generation with centre-based PWM generation and equal PWM frequency, see use cases above and access more than one PWM channel by the same PWM Generation driver block and set the Period-Compare of all PWM channels to the same value.
  • If logic is used in the Simulink model, PWM generation can be accomplished which also can deal with duty cycles of 0 and 1 exactly, by setting the A-output Stop State and B-output State values accordingly and then set the PWM generation to mode Stopped. As soon as the duty cycle ‘moves’ away from 0 or 1 to a value in between, the PWM generation is then set to mode Started again.

The A and B signal outputs are equipped with protection logic. The protection logic avoids, if needed, that the A and B output signals become both High at any given time as soon as the associated I/O pins have been set to outputs by the driver. The Protection value defines the behavior of the protection logic if A and B become both High:

  • 0: Protection turned off, the A and B signals ‘keep’ their values
  • 1: Protection turned on, the A signal is set to Low and the B signal ‘keeps’ its value
  • 2: Protection turned on, the B signal is set to Low and the A signal ‘keeps’ its value
  • 3: Protection turned on, the A signal and B signal is set to Low

Beside the A-Output and B-Output signals, the PWM generation provides a third output signal which is called Trigger and can be used to trigger/control other I/O components like A/D converters. The Trigger-Output signal outputs a High pulse for a defined duration (Trigger Pulse Length) based on the Trigger Source value:

  • 0: If the Counter value is equal to count 0
  • 1: If the Counter value is equal to Period-Compare
  • 2: If the Counter value is equal to A-Compare
  • 3: If the Counter value is equal to B-Compare

The pulse starts one count after the equality is true. The Trigger Pulse Length value for a given duration (T) in seconds can be calculated as Trigger Pulse Length= round( 33e6 * T) -1

The Trigger Pulse Length can have a value between 1 and 255 and can therefore define a maximum pulse duration of 7.757 microseconds.

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