Configurable FPGA I/O modules
Each FPGA-based I/O module includes a Xilinx FPGA chip to implement and execute functionality which typically can't be met by fixed-functionality I/O modules and to achieve highest cycle-rate inner control loop implementations. The wide range of tranceiver types supported by the 3xx I/O modules allow you to connect your design with your hardware.
Key functionality provided by the FPGA I/O modules
- Digital pulse train generation and capture implementations for:
PWM, Capture, Quadrature Decoding, … - Event-based interrupt, trigger, and inversion support
- Inter-system, -sensor/actuator, and -chip protocols (SPI, I2C, …)
- Generic digital inputs and outputs
- Analog I/O with lowest latency and/or special synchronization schemes
- Highest cycle-rate algorithmic implementations of system designs in combination with above functionality for very fast inner control loops
There is no need for you to deal with FPGA programming unless you decide to implement FPGA functionality on your own using Speedgoat's FPGA engineering kits or other tools.
Because FPGAs run at much higher 'speeds' than software-based designs they are also ideal to implement and co-execute very fast algorithmic subsystems on the configurable FPGA I/O module together with the upper level 'slower' dynamics on a software-based system (CPU) to further increase sample rates. Configurable FPGA-based I/O modules are therefore oftentimes an excellent alternative to other 'fast' DSP or Microcontroller based subsystems.
Overview FPGA-based I/O modules
| I/O module | FPGA chip | # logic cells | Standard I/O lines |
| IO301 | Xilinx Virtex-II | 7k | 64 TTL |
| IO302 | Xilinx Virtex-II | 7k | 32 RS422 |
| IO303 | Xilinx Virtex-II | 7k | 16 TTL and 24 RS422 |
| IO304 | Xilinx Virtex-II | 7k | 32 LVDS |
| IO311 | Xilinx Virtex-II | 24k | 64 TTL |
| IO312 | Xilinx Virtex-II | 24k | 32 RS422 |
| IO313 | Xilinx Virtex-II | 24k | 16 TTL and 24 RS422 |
| IO314 | Xilinx Virtex-II | 24k | 32 LVDS |
| I/O module | FPGA chip | # logic cells | Standard I/O lines |
Auxiliary I/O lines (basic module) |
|
| IO322 | Xilinx Virtex-4 | 41k | 30 RS485 | 56 LVCMOS plus 4 LVDS or 32 LVDS | |
| IO323 | Xilinx Virtex-4 | 41k | 16 TTL and 22 RS485 | 56 LVCMOS plus 4 LVDS or 32 LVDS | |
| IO324 | Xilinx Virtex-4 | 41k | 30 LVDS | 56 LVCMOS plus 4 LVDS or 32 LVDS | |
| IO325 | Xilinx Virtex-4 | 41k | 2 16-bit 105MHz A/D signals | 56 LVCMOS plus 4 LVDS or 32 LVDS |
By default (in price included) Speedgoat implements the following set of FPGA Code Modules for the IO301-IO324: 3 x PWM, 3 x CAP, 3 x QAD, 1 x Interrupt, and 1 x Inversors. The remaining I/O lines provide support for generic digital inputs or outputs.
Other configuration as well as FPGA-based protocols or algorithmic designs can be implemented on request.
Use Cases
A frequent use case of configurable FPGA-based I/O modules is the provision of generic and more special pulse train functionality such as PWM, capture, quadrature decoding, and generic digital I/O. This functionality is available to engineers either as an option configured by Speedgoat or for advanced users as configurable code modules.
The majority of configurable FPGA I/O modules provide digital I/O lines, but Speedgoat also covers configurable FPGA I/O modules with analog frontends providing very fast A/D and D/A I/O together with digital I/O e.g to form high speed inner current control loop for motion control applications.
FPGA implementation services
Speedgoat designs FPGA code modules and implements algorithmic subsystems to a broad range of configurable FPGA I/O modules with Virtex Xilinx chip according to your requirements.
How to proceed
Contact Speedgoat to discuss whether the use of configurable FPGA I/O modules could be a promissing approach for your application.
Customer quote
"Up and running in less than a day!"
Darren Hartman,
HUSCO International
News
New I/O Expansion chassis with six additional PCI slots
(03-May-2010) Read more
New Quadrature Decoding FPGA code module complementing the PWM and CAP FPGA code modules
(27-Apr-2010)
Read more
New SPI and I2C FPGA-based configurable protocol support
(12-April-2010)
Read more
New Education real-time target machine for mechatronic designs
(01-Mar-2010)
Read more
Raw Ethernet, UDP, J1939, Arinc 429, MIL-STD-1553, Shared Memory, LVDT/ RVDT, and Synchro/ Resolver support (01-Jan-2010) Read more
xPC Target dual core and highest CPU clockrate support (3.33GHz) (04-Sep-2009) Read more
Newsletter subscription