
IO301
Configurable FPGA-based I/O module with 64 TTL I/O lines and Xilinx Virtex-II chip with 7k logic cells.
This I/O module provides a total of 64 TTL I/O lines and is based on configurable FPGA technology (Xilinx Virtex-II with 7k logic cells) allowing Spedgoat to implement project specific functionality including:
- Pulse train capture and generation:
PWM, CAP (Capture), QAD (quadrature decoding) - Event-based interrupt, trigger, and inversion support
- Protocols (SPI, I2C, ..)
- Generic digital inputs and outputs
- High-speed algorithmic subsystems (system design implementations)
- Analog I/O with lowest latency and/or special synchronization schemes
By default (in price included) Speedgoat implements the following FPGA Code Modules:
3 x PWM, 3 x CAP , 3 x QAD,
1 x Interrupt, 1 x Inversor, and 38 x DIO.
An implementation different from the setup outlined above can be developed and provided at the time of the I/O module purchase or at a later time.
Note that each implemented FPGA Code Module reduces the no. of available I/O lines and logic cells, additional restrictions may apply:
|
Code module |
Min./Max. no. of selectable code modules | Required TTL I/O lines per code module | Required FPGA chip space per code module |
| PWM | 2...m in steps of 2 | 3 (outputs - A, B, Trigger) | 11% |
| CAP | 2...n in steps of 2 | 1 (input) | 6% |
| QAD | 2...j in steps of 2 | 3 (inputs - A, B, Index) | 11% |
| SPI | 1...p in steps of 1 | 6 (master or slave) | 10% |
| DIO | 2...k in steps of 2 | 1 | 0% |
| Interrupt | 1....q in steps of 1 | 2 | 4% |
| Inversor | 1....r in steps of 1 | 2 | 1% |
Formula to calculate the selectable code module mix and remaining FPGA space:
m x 3 + n x 1 + j x 3 + p x 6 + k x 2 + q x 2 + r x 2 <= 64 lines and
m x 11% + n x 6% + j x 11% + p x 10% + q x 4% + r x 1% <= 100%.
If you require more FPGA chip space have a look at the IO311. If you require I/O lines providing different transeiver types have a look at the IO302-304, IO312-314, and 32x series.
Each IO301 I/O module comes with xPC Target driver blocks and Simulink test models, an external shielded 68-pin I/O cable and a terminal board for easy access of all physical I/O signals, and comprehensive documentation.
This I/O module in the PMC form factor and can be used in any Speedgoat real-time target machine with the exception of the Classic real-time target machine.
Contact Speedgoat to receive further information about this and other 3xx series I/O modules and to discuss your requirements.
Customer quote
"Up and running in less than a day!"
Darren Hartman,
HUSCO International
News
Automatic HDL code generation for Speedgoat's FPGA-based I/O modules for Real-Time Simulation and Testing on FPGAs
(08-April-2011) Read more
Performance real-time target machine now supports i5 multi-core CPUs with clock rates up to 3.6GHz
(08-April-2011) Read more
Mobile real-time target machine now supports dual-core CPUs with clock rates up 2.16GHz
(14-March-2011) Read more
New 18-bit analog input I/O module with up to 32 channels
(03-January-2011) Read more
MathWorks and Speedgoat launch xPC Target Turnkey solution(25-August-2010) Read more
Newsletter subscription