IO325Configurable FPGA-based I/O module with 2 x 16-bit 105MHz A/D, 56 LVCMOS/4 LVDS or 32 LVDS auxiliary I/O lines, and Xilinx Virtex-4 chip with 41k logic cells.
This configurable I/O module is based on FPGA technology allowing Spedgoat to implement project specific functionality including:
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By default (in price included) Speedgoat implements the standard FPGA Code Module functionality for the 2 16-bit 105MHz A/D lines as described below.
Additional FPGA Code Module functionality can be developed and implemented on the Auxiliary I/O. Note that each implemented FPGA Code Module reduces the no. of available I/O lines and logic cells. Additional restrictions may apply.
Standard I/O (2 16-bit 105MHz A/D)
The 2 lines allow you to convert analog inputs to digital representations, where as the input signal is evaluated each 1/(105x10^6) [s] to generate a numerical value. Values between -1.7[V] and +1.7V are encoded on 16 bits.
An input voltage of 1.7 is represented by a numeric value of 32767, and an input voltage of -1.7 by a numeric value of -32768.
Typically such functionality is required for HIL systems requiring support for current or voltage control by using a PI (proportional-integral) controller.
Auxiliary I/O (56 LVCMOS/4 LVDS or 32 LVDS)
Note that the use of the auxiliary I/O lines requires a special PMC-to-PCI carrier and additional signal conditioning equipment.
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Code module |
Min./Max. no. of selectable code modules | Required LVCMOS/LVDS lines per code module | Required FPGA chip space per code module |
| PWM | 2...m in steps of 2 | 3 (outputs - A, B, Trigger) | 1.9% |
| CAP | 2...n in steps of 2 | 1 (input) | 1.0% |
| QAD | 2...j in steps of 2 | 3 (inputs - A, B, Index) | 1.9% |
| SPI | 1...p in steps of 1 | 6 (master or slave) | 1.9% |
| DIO | 2...k in steps of 2 | 1 | 0% |
| Interrupt | 1....q in steps of 1 | 2 | 0.8% |
| Inversor | 1....r in steps of 1 | 2 | 0.2% |
Formula to calculate the selectable code module mix and remaining FPGA space:
m x 3 + n x 1 + j x 3 + p x 6 + k x 2 + q x 2 + r x 2 <= 60/32 lines and
m x 1.9% + n x 1.0% + j x 1.9% + p x 1.9% + q x 0.8% + r x 0.2% + chip space required for FPGA Code Modules requiring I/O lines of the standard I/O <= 100%.
Each IO325 I/O module comes with xPC Target driver blocks and Simulink test models, an external shielded 68-pin I/O cable and a terminal board for easy access of all physical I/O signals, and comprehensive documentation.
This I/O module in the PMC form factor and can be used in any Speedgoat real-time target machine with the exception of the Classic real-time target machine.
Contact Speedgoat to receive further information about this and other 3xx series I/O modules and to discuss your requirements.
Customer quote
"Up and running in less than a day!"
Darren Hartman,
HUSCO International
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