I2C Protocol Support

To communicate with I2C (Inter IC-Bus) devices Speedgoat can implement I2C FPGA code modules providing I2C protocol and controller functionality on any of the configurable FPGA-based IO3xx series I/O modules.

I2C FPGA Code Module - Key features
The implemented I2C protocol supports 64 registers including 8-bits each which can be addressed with a pointer (subaddress). The pointer consists of 8-bits: the MSB (most significant bit) to enable or disable the auto-increment function, and the 7 LSB (least significant bits) to define the address of the initial register.

The included Simulink Blocksets support the following operations (see also communication frames below):

1. Single write
2. Multiple write
3. Single read
4. Multiple read

The Simulink Blocksets also allow you to define which registers you want to read or write.

Communication Frames - Legend:
SAD: Slave address, W: Write mode, R: Read mode, SAK: Slave acknowledge, NMAK: no Master acknowledge, MAK: Master acknowledge, SR: Start Repeated condition

Note that in read mode, a correct acknowledge always has a value of zero. Furthermore the last acknowledge signal (NMAK) is a non-acknowledge with a value of high, even in case the last received byte is correct. The reason of this polarity is because of the PULL-UP resistor having a standard value of high whenever the I/O module uses no line.

Contact us if you require other protocol support. Speedgoat continuously extends the range of supported communication bus types and devices.

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