Event based interrupt support for IO3xx FPGA I/O modules

Each Speedgoat FPGA-based I/O module comes by default with Interrupt generation support for the PWM FPGA Code Module to execute your models either at the high to low or the low to high transition events instead of having the execution based on the CPU timer.

Other interrupt generation events for the PWM and other FPGA Code Modules for example in case a tasks completes, reaches a specific stage, or an error occurs, can be implemented on request.

The standard Interrupt implementation requires one input line and requests the interrupt (#intA) as defined in the provided xPC Target driver blockset:



Supported parameter settings:

Debounce duration: defines the duration where the interrupt input signal is tested. If the signal is stable for such a time, the FPGA estimates it is a valid signal and asserts the interrupt. Maximum value is 2^10 - 1. Write 0 in this field to turn off the feature.

Interrupt delay: the board can delay the interrupt before its assertion. Correct values are from 0 to 2^20 - 1.

Polarity: FPGA can assert interrupt when the input signal is rising (then the parameter must be set to 0) or falling (then the parameter must be set to 1).

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