PWM Code Module for IO3xx FPGA I/O modules

At its core the PWM (Pulse Width Modulation) FPGA code module contains a 32-bit deep counter clocked at 33MHz and the PWM control logic. This code module requires three digital I/O lines (A-Output, B-Output, Trigger-Output) set as output. Together, lines A, B, and the Trigger form a PWM channel.

The PWM FPGA code module can be implemented on all
IO3xx series configurable FPGA I/O modules.

Key functionalities supported by the PWM code module include:

• symmetric, asymmetric, single-phase, multi-phase, and deadband compensation
• frequency-modulated pulse trains

Functional description



Pulse train generation is based on a counter comparison having two pulse train signals (line A and line B) which share the same period but with a different duty cycle and a trigger.

To define your train pulses the following parameters can be set:

• C: Half-period length
• A: compare value
• B: compare value

The above graph illustrates an example including a blue dashed line representing the counter behavior incrementing until the half-period and then decrementing to zero again and lines A and B representing customer defines pulse train duty cycles using the A and B parameter values.

The A and B duty cycles are centered at the half-period and are therefore symmetric. Furthermore both, the A and the B values are equal to the counter values once during its incrementation and once during its decrementation.

A and B comparison values can be different, but always share the same counter period.

Each time the counter reaches the A or A' respectively B or B' value one of the following actions can be set and performed:

• Toggle: The signal is inversed
• Force signal to one: The signal becomes one
• Force signal to zero: The signal becomes zero
• No action: The signal keeps the same state

Actions for A, A', B, and B' can be set independently. For instance the signal is set at one when the counter is equal to A and set to zero when the counter reaches A'.

All parameters can be changed during model run-time and take effect whenever the counter starts a new period.

Specifications
PWM code module base frequency: 33MHz (can be set to 66MHz by Speedgoat)

HalfPeriod: (T * F)/2
T = user period in [s]
F = PWM code module frequency (33MHz or 66MHz)

Maximal signal resolution: 1/F = 30.30ns (15.15ns if base frequency is set to 66MHz)

Example
If a customer want to achieve a frequency of 40KHz (= period of 25µs) and accuracy of 0.001%, the base frequency needs to be set by Speedgoat to 66MHz and the HalfPeriod value parameter needs to be set to 825 (25*10^-6*66*10^6)/2).

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