Motion Control FPGA package
| Summary |
| Multi-purpose FPGA-based I/O module with 64 TTL I/O lines and Xilinx Virtex-II chip with 7k or 24k of logic cells implementing 3 channels for PWM generation, 3 channels for PWM capture, 3 channels for quadrature decoding of incremental encoder sensors, 1 Interrupt, 1 Negation, and 36 digital I/O channels configurable as inputs or outputs in pairs of two. Delivery includes I/O cable, terminal board, and Speedgoat drivers and blocksets for Simulink and xPC Target. Installed in Education real-time target machine and fully tested. Can not be combined with Education CAN I/O package. |
| I/O subsystem | |
| I/O module | 32-bit 33MHz I/O module with 64 TTL lines for PWM, CAP, ENC, and DIO. Including reconfigurable FPGA to develop and implement custom FPGA functionality. |
| Direction | I/O lines individually programmable as inputs or outputs in groups of two |
| V-out-high | 3.8V minimum |
| V-out-low | 0.55V maximum |
| I-out-high | -32mA |
| I-out-low | 32mA |
| V-in-high | 3.5V minimum |
| V-in-low | 1.5V maximum |
| Software | |
| Code modules | Fixed Speedgoat FPGA code modules channel implementation for PWM, capture, quadrature decoding, interrupt, negation, and generic digital I/O. |
| Drivers | Speedgoat tools and drivers for xPC Target |
| Test models | Simulink test models |
| V-out-high | 3.8V minimum |
| Accessories | |
| Terminal block | Terminal block containing 64 terminal. The terminal block can either be placed on a working desk or mounted onto a DIN rail and simplifies getting started with the I/O module by allowing to easily plug and unplug wires carrying the electrical signals for testing. |
| Cable | Round shielded 1.8m/6ft 68-pin I/O cable with male connectors at both ends |
| Documentation | I/O module and FPGA Code Module functionality and driver blocks description for PWM, Capture (CAP), Quadrature Decoding (QAD), Interrupt (INT), Negation (NEG), and generic digital I/O (DIO), and I/O pin mapping. |
Customer quote
"Up and running in less than a day!"
Darren Hartman,
HUSCO International
News
Automatic HDL code generation for Speedgoat's FPGA-based I/O modules for Real-Time Simulation and Testing on FPGAs
(08-April-2011) Read more
Performance real-time target machine now supports i5 multi-core CPUs with clock rates up to 3.6GHz
(08-April-2011) Read more
Mobile real-time target machine now supports dual-core CPUs with clock rates up 2.16GHz
(14-March-2011) Read more
New 18-bit analog input I/O module with up to 32 channels
(03-January-2011) Read more
MathWorks and Speedgoat launch xPC Target Turnkey solution(25-August-2010) Read more
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