Motion Control FPGA Package

The Motion Control FPGA package extends the Education real-time target machine with an I/O module and complementing Speedgoat FPGA code modules to study and teach advanced mechatronic.

Key components of the Motion Control FPGA Package

• 32-bit 33MHz PMC I/O module with 64 TTL I/O lines and Xilinx Virtex-II chip, including passive PMC-to-PCI carrier
• FPGA code module implementation (bitstream) for PWM, Capture, Quadrature Decoding, and generic digital I/O (see below)
• Cable and terminal board
• xPC Target driver blocks and Simulink test models

Speedgoat configures the Xilinx Virtex-II chip with 7k logic or 24k logic cells (selectable) with the following set of pulse train capture and generation functionality:

• PWM: 3 channels for PWM signal generation (asymetric, symetric, centered, single-phase, multi-phase, deadband compensation) and frequency-modulated pulse trains
• CAP: 3 channels for measuring pulse duration, period duration, and PWM duty-cycle
• QAD: 3 channels for quadrature decoding of incremental encoder sensor inputs
• INT: 1 interrupt such as for synchronization with analog I/O channels
• DIO: 36 generic digital I/O lines)

Custom FPGA design concepts
To develop your own FPGA designs you can do so using the Education FPGA Development Guide for xPC Target including a step-by-step industruction, VHDL code examples, and Simulink blocks for FPGA bitstream-download and FPGA application interaction.

• HOME
• Products

• Real-time target
  machines

• Performance
• Mobile
• Modular
• Education

• Study & teach
• Visual overview
• Chassis/mainboard
• I/O subsystem
• Motion Control
  FPGA package
• xPC Target
• Data sheet
• Ordering & Price

• Audio
• Automation
• Classic
• Basic

• I/O modules

• Services
• Applications
• Customers
• Industries
• Support
• Exchange area
• Company