Motion Control FPGA Package

The Motion Control FPGA package extends the Education real-time target machine with an additional I/O module and complementing Speedgoat FPGA Code Modules to study and teach advanced mechatronic.

Key components of the Motion Control FPGA Package

  • Multi-functional motion control I/O module with 64 x 3.3V/5V digital TTL lines and Xilinx Spartan 6 chip with 50k logic cells
  • FPGA Code Module implementation (bitstream) for PWM, Capture, Quadrature Decoding, and generic digital I/O (see below)
  • Cable and terminal board
  • Simulink Real-Time driver blocks and Simulink test models

Speedgoat configures the Xilinx Spartan 6 chip with the following set of pulse train capture and generation functionality:

  • PWM: 3 channels for PWM signal generation (asymetric, symetric, centered, single-phase, multi-phase, deadband compensation) and frequency-modulated pulse trains
  • CAP: 3 channels for measuring pulse duration, period duration, and PWM duty-cycle
  • QAD: 3 channels for quadrature decoding of incremental encoder sensor inputs
  • INT: 1 interrupt such as for synchronization with analog I/O channels
  • DIO: 40 generic digital I/O lines

Custom FPGA design concepts
You can develop your own FPGA designs using the Education FPGA Development Guide for Simulink Real-Time which includes step-by-step instructions, VHDL code examples, and Simulink blocks for FPGA bitstream-download and FPGA application interaction.

I/O subsystem
I/O module 32-bit 33MHz I/O module with 64 TTL lines for PWM, CAP, ENC, and DIO. Including reconfigurable FPGA to develop and implement custom FPGA functionality.
Direction I/O lines individually programmable as inputs or outputs in groups of two
V-out-high 3.8V minimum
V-out-low 0.55V maximum
I-out-high -32mA
I-out-low 32mA
V-in-high 3.5V minimum
V-in-low 1.5V maximum
Code modules Fixed Speedgoat FPGA Code Modules for PWM, capture, quadrature decoding, interrupt, negation, and generic digital I/O.
Drivers Speedgoat tools and drivers for Simulink Real-Time
Test models Simulink test models
V-out-high 3.8V minimum
Terminal block Terminal block with 64 terminals. Can either be placed on a desk or mounted on a DIN rail. The terminal block allows signal wires to be easily connected.
Cable Round shielded 1.82m (6ft) 68-pin I/O cable with male connectors at both ends
Documentation Documentation is provided for the I/O module, the FPGA Code Modules, and driver blocks for PWM, Capture (CAP), Quadrature Decoding (QAD), Interrupt (INT), Negation (NEG), and generic digital I/O (DIO).
Item ID Product Name Description
108007 Motion Control FPGA package Flexible FPGA-based I/O module with 64 TTL 3.3V/5V I/O lines and Xilinx Spartan 6 chip with 50k logic cells. Includes I/O cable, terminal board, and Speedgoat driver blocksets and FPGA bitstream for Simulink Real-Time implementing the following default set of FPGA Code Modules:
  • 3 x PWM (pulse train generation)
  • 3 x CAP (capture)
  • 3 x QAD (quadrature decoding of incremental encoder sensors)
  • 1 x INT (interrupt)
  • 1 x Negation
  • 40 x DIO (generic digital I/O) channels selectable as inputs or outputs in pairs of two

Pricing information and product evaluation support
As your project might be complex, we believe that it is best to first phone or e-mail to evaluate your requirements. Based on this, we will be able to make sure you receive product and pricing information for your ideal real-time target solution. We are fast-reacting and are happy to discuss your requirements with you, so you won't lose time, but will profit from our professional evaluation service.

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